1. Field of the Invention
The present invention relates to a reference electric potential generating circuit of a ferro-electric random access memory, and in particular, is used for a ferro-electric random access memory structured from a one-transistor and one-capacitor (1T1C) type memory cell which is suitable for high-integration.
2. Description of the Related Art
The ferro-electric random access memory has the features that it stores data in a nonvolatile manner, and that the reading/writing speed thereof is as high-speed as that of DRAMs and SRAMs, and it is one of the memories which is currently being most noticed.
With respect to DRAMs, currently, products having memory capacities of 128 megabits to 512 megabits are being merchandised. However, with respect to ferro-electric random access memories, the history thereof is not long, and merely the development of products having a memory capacity of 32 megabits has been announced at academic conference.
With respect to ferro-electric random access memories as well, it is thought that the increasing of the memory capacity thereof will progress from now on. However, what is problematic here is reducing the cell surface area.
In a conventional ferro-electric random access memory, in order to achieve a stable operation, a two-transistor and two-capacitor (2T2C) type memory cell is used. The 2T2C type memory cell is a memory cell of a type in which 1 bit data is stored by using two transistors and two capacitors.
It can be said that the 2T2C type memory cell is a memory cell in which 1 bit data is stored by using two of the 1T1C type memory cells. In this case, the data stored in one of the 1T1C type memory cells and the data stored in the other 1T1C type memory cell are set so as to have values which are opposite to one another. Further, because the data reading is carried out due to both of the data being compared with one another, a stable reading is possible.
However, in the 2T2C type memory cell, because the number of elements required for storing 1 bit data is large, the surface area on a chip required for 1 bit is large of necessity, and the 2T2C type memory cell is not suitable for increasing memory capacity.
Then, currently, mainly, the development of ferro-electric random access memories using 1T1C type memory cells has been carried out. The 1T1C type memory cell is a memory cell of a type in which 1 bit data is stored by using one transistor and one capacitor, and because the data reading is carried out by comparison between an electric potential of reading of the memory cell and a reference electric potential, the 1T1C type memory cell is suitable for achieving increasing memory capacity.
These are described in the following documents.
Document 1:
ISSC94/SESSION 16/TECHNOLOGY DIRECTIONS: MEMORY, PACKAGING/PAPER FA 16.2: A 256 kb Nonvolatile Ferroelectric Memory at 3V and 100 ns: Sumi et al.
Document 2:
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, No. 5, MAY 1997: 2-V/100-ns 1T/1C Nonvolatile Ferroelectric Memory Architecture with Bitline-Driven Read Scheme and Nonrelaxation Reference Cell: Hirano et al.
FIG. 1 shows an example of a cell array portion of the conventional ferro-electric random access memory structured from a 1T1C type memory cell.
A memory cell MC and a dummy cell DC are disposed in a cell array portion CA.
The memory cell MC is structured from a selective transistor ST and a ferro-electric capacitor CC. The selective transistor ST and the ferro-electric capacitor CC are connected in series. One end of the selective transistor ST is connected to a bit line BL1, and a plate electric potential VPL is supplied to one end of the ferro-electric capacitor CC. A gate of the selective transistor ST is connected to a word line WL.
At the time of the reading operation, when the word line WL is selected, a pressurizing electric potential VPP, for example, about 4V is supplied to the word line WL. The plate electric potential VPL at this time is set to, for example, about 2.5V.
The dummy cell DC is structured from selective transistors DT1 and DT2, a reset transistor RST, and a paraelectric capacitor DCC. The selective transistor DT1 is connected between the bit line BL1 and one end of the paraelectric capacitor DCC, and the selective transistor DT2 is connected between the bit line BL2 and the one end of the paraelectric capacitor DCC.
The gate of the selective transistor DT1 is connected to a dummy word line bDWL, and the gate of the selective transistor DT2 is connected to a dummy word line DWL. One end of the reset transistor RST is connected to the one end of the paraelectric capacitor DCC, and an earthing electric potential Vss is supplied to the other end of the reset transistor RST. The turning-on/turning-off of the reset transistor RST is controlled by a control signal BDRST. A dummy plate electric potential DPL is supplied to the other end of the paraelectric capacitor DCC.
Here, for example, when data of the memory cell MC is read at the bit line BL1, a reference electric potential generated by the dummy cell DC is supplied to the bit line BL2. Namely, an electric potential at the one end of the paraelectric capacitor DCC is risen to a predetermined value by coupling with the dummy plate electric potential (an electric potential at the other end of the paraelectric capacitor DCC, for example, about 1.5V) DPL. Further, the dummy word line DWL becomes “H”, and the dummy word line bDWL becomes “L”.
A sense amplifier SA is connected between the bit lines BL1 and BL2. The sense amplifier SA has a P channel sense amplifier formed from two P channel MOS transistors QP1 and QP2, and an N channel sense amplifier formed from two N channel MOS transistors QN1 and QN2. The P channel sense amplifier is controlled by a control signal BSEP, the N channel sense amplifier is controlled by a control signal SEN.
An operating electric potential VAA of the sense amplifier SA is usually set to the same electric potential (for example, about 2.5V) as the plate electric potential VPL of the ferro-electric capacitor CC. CB is wiring capacity generated in the bit lines BL1, and BL2.
FIG. 2 shows a cell distribution diagram showing a bit number (a number of memory cells) on the abscissa and an electric potential of a bit line on the ordinate.
VBL is the distribution of an electric potential (signal amount) of a bit line when “0” is read from the memory cell, and VBH is the distribution of an electric potential (signal amount) of a bit line when “1” is read from the memory cell, and VRef is the distribution of an electric potential (signal amount) of a bit line when the reference electric potential is read from the dummy cell.
The reason that such distributions arise with respect to VBL, VBH, and VRef is that dispersion in manufacturing arises with respect to the dimensions, the thickness, and the like of the cell capacitor (the ferro-electric capacitor or the paraelectric capacitor).
In order to correctly determine “1” and “0” in a sensing operation at the time of reading, for example, it is ideal that the average value of the VRef distribution (the median value between the maximum value and the minimum value of the VRef distribution) is set to the median value (the tip of an arrow 62) between the maximum value of the VBL distribution (the tip of an arrow 61) and the minimum value of the VBH distribution (the tip of an arrow 63) (ΔH=ΔL).
However, with respect to ferro-electric capacitors in particular, the characteristics thereof greatly vary due to changes in reliability over time, manufacturing dispersion of the dimensions, the thickness, and the like, variations in the operating environment (for example, temperature), and the like. For example, as shown by the broken line of FIG. 2, there are cases in which the VBL distribution is shifted from the ideal position to the VBH side due to these factors.
In this case, a margin between the maximum value of the VBL distribution and the average value of the VRef distribution becomes insufficient, and the probability of a malfunction arising with respect to the “0” reading is high.
Further, if the VRef distribution is made to shift to the VBH side, and a sufficient margin is ensured in order to prevent the malfunction with respect to the “0” reading in this case, a margin between the minimum value of the VBH distribution and the average value of the VRef distribution becomes insufficient. As a result, the probability of a malfunction arising with respect to the “1” reading is high.
As described above, in the prior art, a proposal for a 1T1C type ferro-electric random access memory, which can always ensure a sufficient margin between the electric potential of the bit line corresponding to the read data and the reference electric potential without being affected by changes in reliability over time, manufacturing dispersion of the dimensions, the thickness, and the like, variations in the operating environment, or the like of a ferro-electric capacitor, has been desired.